Until recently any thoughts of implementing a Sytem On a
Chip have been restricted to those considering ASIC
Over the last few years there have been major developments in FPGA logic density, speed, packaging etc.
These have made implementing a 'system' of processor/s, IP blocks, user logic in an
FPGA (System On a Programmable Chip) a possiblility . Indeed, with potentially large complex designs
FPGA implementation can be more attractive as it carries few of the risks of ASIC implementation.
Even the recently introduced low-end/cheap FPGA families have the resources to implement a simple CPU core.
Anyone starting a design with an embedded processor with any amount of application
specific logic ought to consider whether a SOPC might provide a better solution.
The main SOPC advantage is flexibility.
A RISC CPU core can be configured to be 16/32 bits, have data or instruction pipelining,
hardware multipliers, custom instructions with hardware acceleration to increase system performance. Typically
this can run at speeds of up to 100MHz (see below for real world examples).
Also, whatever peripherals that are needed can be included. Six UARTS, ten I2C channels,
LVDS interfaces, an SDRAM controller etc, whatever the application demands.
Typically a large portion of the FPGA resource is left for aplication logic.
In the smallest device in Altera's most recent low cost FPGA family (Cyclone 1C3), a minimal 16 bit CPU
will occupy approximately 50% of the device logic. In the largest devices even a complex
32 bit CPU core will occupy less than 5% of the device logic.
The flexibility of an FPGA SOPC implementation gives some protection against
feature creep after a PCB has been designed, and opens the possibility of
one PCB being used in multiple applications depending on its configuration.
Implementing a system in a programmable device gives significant protection against
obsolescence. FPGA families are supported by the manufacturers for years. Due
to their nature a small number of devices can be used for a multitute of
purposes, so FPGA vendors don't have to build and stock a large number of
differently configured devices. This economy of scale means that devices
that are over ten years old are still available. As FPGA use increases and
devices win more design-ins this situation is likely to continue.
If an FPGA does go obsolete as the SOPC is a soft core it can be re-targeted
at a new family of FPGA. No software need be re-written/modified etc.
SIMPLER BOARD DESIGN
As the interconnections between different modules in a system are mostly internal
to the FPGA the number of high speed signals radiating is vastly reduced. Clock
distribution and inter chip timing problems are also removed, internal PLLs
can remove the need to distribute high speed clocks round a PCB, making EMC
tests much more likely to be passed first time.
termination problems and so on are also removed for any modules in the FPGA.
As a result a PCB can be smaller, consume less power, be easier to get through
EMC tests and more likely to work first time.
PCBs with one large device rather than several smaller ones can be smaller,
easier and cheaper to kit, manufacture and test.
To help with board test dedicated test designs can be loaded into the FPGA
to automate testing. This is not nearly as easily done with an ASIC.
If significant application logic is needed a controlling uP core can be
had almost for free. A 16 bit CPU core can take less than 2% of the logic in
the largest devices.
Depending on the application the FPGA/SOPC configuration and firmware can be remotely updated (the
Cyclone configuration devices can hold the programme/data for a CPU core and both the FPGA
configuration and program can be updated by the FPGA).
FPGA's tend not to be suitable for very low power applications and most modern devices require two
or three power supplies and ground, usually supplied via multiple planes.
Implementing a complex system in an FPGA is not a simple task, especially without
previous experience of the family/design tools.
Incorporating a number of modules in a single package can force the use of a BGA
package to provide the required number of IO pins. If BGA packages hadn't been planned
for the PCB this may lead to a more expensive build and more difficult re-work.
If an application includes a requirement for an A/D convertor this must be implemented
with an external IC. D/A convertors can be implemented with PWM output on a pin with
a low pass filter, and a basic A/D convertor can use this output with a comparator,
but any requirement for speed/accuracy usually dictates external components.
As their FPGAs have become more capable of system on a chip implementation
Altera have addressed certain problems that arise. They have introduced a
configurable CPU soft core, NIOS, together with a tool, SOPC Builder, to manage the complexity
of defining the CPU and integrating the software, with custom peripherals, user logic and
This is a 16/32 bit risc processor soft core which comes with many available peripheral components.
The CPU can be configured to inlude a hardware multiplier, data and instruction
caches, hardware debug ports, interrupt support, hardware divide etc depending on
User logic is easily interfaced with the core. A Wizard is available to examine the interface code and
attempt to deduce functionality, or this can be specified manually
The peripherals which are immediately available are..
Also available as IP cores from Altera are...
- SPI interface
- AMD 29LV065 Flash
- LAN91C111 Ethernet interface (10/100 MAC)
- SDRAM controller
- DMA controller
- Interval Timer
- Parrallel IO interface
- User Logic IF
- TCP/IP Software stack
- CAN 2.0 Network controller
- I2C master/slave interfaces
- T1 framer
- 10/100/1G Ethernet MAC
- PCMCIA Compact Flash Controller
- USB 2.0 Controller
The NIOS CPU is supported by the GNUPro C/C++ toolkit which is becoming an industry standard
toolset. A C/C++ compiler, an assembler, linker, and GDB source and assembly level debugger
(with Insight GUI front end) are included.
If we deliver a SOPC design based on a NIOS CPU a client can then use the GNU tools
to write/debug software and re-programme application FLASH (if included) as if using normal
embedded processor. (The NIOS GNUPro tools can be directly downloaded from Altera).
When a system has been configured then generated, the SOPC builder generates an RTL description
of the CPU and peripherals and a Software Development Kit (SDK) configured for this core. The SDK
includes header files defining the memory map and all peripherals, a library of example
drivers for the peripherals included and a series of example source files and a make files
which may be used for debugging.
A modelsim environment is also created to allow the complete SPOC to be modelled prior
Once the CPU and interfaces to application logic are defined software development can start
immediately, allowing simultaneous hardware and software development.
Some examples of SOPC configurations/devices and speeds are...
Cyclone (-7 speed grade): Includes 32-bit Nios with 4K iCache & dCache,
hardware multiply, JTAG-based "OCI" comm/debug port, boot
ROM, SDRAM controller, SRAM/Flash/Ethernet MAC interfaces,
UART, two timers, PIO for the buttons, LEDs, remote reconfiguration,
etc., Compact flash interface, "ASMI" configuration interface
(to low-cost serial flash ROMs).
Requested f-max=50Mhz, actual f-max: 63.8Mhz.
Stratix (-6 speed grade): Includes most of the same peripherals as
above, but without ASMI memory, and with the addition of 64K
of on-chip "M-RAM" memory). Requested f-max=50Mhz, compiled for
"speed" in Quartus, actual f-max: 69.3Mhz
These are very feature rich examples and were simple push button FPGA compiles with no specific constraints
applied, CPUs with fewer external components will run at over 100MHz.
Here are some reviews on experiences with